Camera and Display Interfaces

Goal: Understand the electrical and protocol layers behind CSI (camera), DSI (display), HDMI, and SPI — how data moves physically between sensors, SoCs, and screens.

1. MIPI D-PHY: The Shared Physical Layer

Both CSI-2 (camera) and DSI (display) use the same electrical interface: MIPI D-PHY. Understanding D-PHY once covers both.

1.1 Differential Signaling

D-PHY uses differential pairs — two wires per signal, carrying opposite voltages. The receiver measures the difference between them, rejecting noise that affects both wires equally.

  Transmitter                                Receiver
  ┌──────────┐    Dp ──────────────────── ┌──────────┐
  │  Driver   │──►                    ──►│ Comparator│──► Data
  │           │    Dn ──────────────────── │  (Dp-Dn) │
  └──────────┘                            └──────────┘

  Dp = VCM + Vdiff/2          Noise (N) affects both wires:
  Dn = VCM - Vdiff/2          (Dp+N) - (Dn+N) = Dp - Dn
                               Noise cancels out.

Parameter	D-PHY Spec
Differential swing	200 mV (±100 mV from common mode)
Common-mode voltage	~200 mV (HS mode)
Termination	100 Ω differential at receiver
Rise/fall time	< 0.15 UI (Unit Interval)

The small 200 mV swing (vs 3.3 V for SPI) enables much higher speeds at lower power — but requires careful PCB layout: matched trace lengths, controlled impedance (100 Ω differential), and ground planes.

1.2 Two Modes: LP and HS

Every D-PHY lane operates in two modes:

  ┌──────────────────────────────────────────────────┐
  │  Low-Power (LP) Mode            ~10 Mbit/s       │
  │  ── Single-ended CMOS levels (0 V / 1.2 V)      │
  │  ── Used for: commands, configuration, wakeup    │
  │  ── Power: ~10 µA per lane                       │
  ├──────────────────────────────────────────────────┤
  │  High-Speed (HS) Mode           up to 2.5 Gbit/s │
  │  ── Differential signaling (200 mV swing)        │
  │  ── Used for: pixel data, bulk transfers         │
  │  ── Power: ~5 mA per lane                        │
  └──────────────────────────────────────────────────┘

A transfer starts in LP mode (slow, low power), transitions to HS mode for the payload, then returns to LP. The receiver detects the transition by watching the voltage levels:

  LP-11 → LP-01 → LP-00 → HS-0 → [data stream] → LP-11
  (idle)  (req)   (bridge)  (sync)                 (idle)

This LP/HS switching happens per-frame in DSI and per-line in CSI-2.

1.3 Clock Lane

D-PHY has a dedicated clock lane (one differential pair) that provides the bit clock to the receiver. Data lanes are sampled on both edges of this clock (DDR — Double Data Rate):

  CLK:   ┌──┐  ┌──┐  ┌──┐  ┌──┐
         │  │  │  │  │  │  │  │
     ────┘  └──┘  └──┘  └──┘  └──
              ↑    ↑    ↑    ↑
         Data sampled on both edges (DDR)

  A 500 MHz clock → 1 Gbit/s per data lane

The clock lane also transitions between LP and HS modes. When all lanes are in LP-11, the interface is idle.

1.4 Lane Speeds

D-PHY Version	Max per Lane	Typical Use
D-PHY 1.0	1.0 Gbit/s	Pi 3 CSI/DSI
D-PHY 1.2	1.5 Gbit/s	Pi 4 CSI/DSI
D-PHY 2.0	2.5 Gbit/s	Pi 5 CSI/DSI
D-PHY 2.5	4.5 Gbit/s	High-res cameras

C-PHY: The Alternative

MIPI also defines C-PHY, which uses 3-wire groups (symbols encoded as wire state transitions) instead of differential pairs. C-PHY achieves higher bandwidth per pin but is not used on Raspberry Pi. If you see "C-PHY" in a sensor datasheet, it is not compatible with the Pi's D-PHY receiver.

2. MIPI CSI-2: Camera Interface

CSI-2 carries image data from a camera sensor to the SoC. It runs on D-PHY and adds a packet layer for framing.

2.1 Architecture

  ┌──────────────┐                          ┌───────────────────────────┐
  │ Camera Sensor │                          │  SoC (BCM2712 / BCM2711) │
  │              │   CLK (1 diff pair)       │                           │
  │  Bayer CFA   │──────────────────────────►│  CSI-2 Receiver           │
  │  pixel array │   Data (2 or 4 lanes)     │       │                   │
  │              │──────────────────────────►│       ▼                   │
  │  I2C config  │◄─────────────────────────►│  ISP (Broadcom)           │
  │  (CCI)       │   I2C (2-wire, ~400 kHz)  │  Debayer, AWB, AE, AF    │
  └──────────────┘                           │       │                   │
                                             │       ▼                   │
                                             │  DMA → Frame buffer       │
                                             └───────────────────────────┘

The camera sensor has two interfaces: - CSI-2 (high-speed, uni-directional): carries raw pixel data - CCI / I2C (low-speed, bidirectional): configures sensor registers (exposure, gain, resolution, frame rate)

2.2 Packet Structure

CSI-2 data is packetized. Each line of an image is wrapped in a packet:

  ┌─────────┬──────────┬─────────────────────┬──────────┐
  │  SoT    │  Header  │  Pixel Data Payload │  CRC-16  │
  │ (sync)  │ (32 bit) │  (variable length)  │ (16 bit) │
  └─────────┴──────────┴─────────────────────┴──────────┘

  Header contains:
  ┌────────────┬────────────────┬──────────────┬──────────┐
  │ Data Type  │ Virtual Channel│ Word Count   │ ECC      │
  │ (6 bit)    │ (2 bit)        │ (16 bit)     │ (8 bit)  │
  └────────────┴────────────────┴──────────────┴──────────┘

Data Type	Code	Description
RAW8	0x2A	8-bit Bayer (common for low-cost sensors)
RAW10	0x2B	10-bit Bayer (IMX219, IMX477)
RAW12	0x2C	12-bit Bayer (high-quality sensors)
YUV422-8	0x1E	Pre-processed YCbCr (some USB-bridge cameras)
RGB888	0x24	24-bit RGB (rare for raw sensors)

Virtual Channels allow multiplexing up to 4 independent streams over the same physical lanes (e.g., stereo cameras or sensor + metadata).

2.3 Frame Timing

  Frame Start (FS) ──────────────────────────────────────────
  │
  │  Line 0:   [SoT] [Header] [1920 pixels × RAW10] [CRC]
  │  Line 1:   [SoT] [Header] [1920 pixels × RAW10] [CRC]
  │  ...
  │  Line 1079: [SoT] [Header] [1920 pixels × RAW10] [CRC]
  │
  Frame End (FE) ────────────────────────────────────────────
  │
  │  VBlank (vertical blanking) ── sensor prepares next frame
  │
  Frame Start (FS) ──────────────────────────────────────────

Between lines, the data lanes return to LP mode briefly (HBlank). Between frames, a longer LP period (VBlank) allows the sensor to reset its readout circuitry.

2.4 Bandwidth Calculation

For a 1920×1080 RAW10 sensor at 30 FPS on 2 CSI lanes:

  Pixel data per frame:
    1920 × 1080 × 10 bits = 20,736,000 bits

  Frames per second:
    20,736,000 × 30 = 622,080,000 bits/s ≈ 622 Mbit/s

  Overhead (blanking, headers, sync, ~15%):
    622 × 1.15 ≈ 715 Mbit/s total

  Per lane (2 lanes):
    715 / 2 ≈ 358 Mbit/s per lane

  D-PHY 1.2 max: 1500 Mbit/s per lane → plenty of margin

Sensor	Resolution	Bit Depth	FPS	Lanes	Required BW	Per Lane
IMX219 (Camera v2)	3280×2464	RAW10	15	2	~1.39 Gbit/s	~695 Mbit/s
IMX219 (Camera v2)	1920×1080	RAW10	30	2	~715 Mbit/s	~358 Mbit/s
IMX477 (HQ Camera)	4056×3040	RAW12	10	2	~1.70 Gbit/s	~850 Mbit/s
IMX477 (HQ Camera)	1920×1080	RAW12	40	2	~1.14 Gbit/s	~572 Mbit/s

Why Does My Camera Only Do 15 FPS at Full Resolution?

The IMX219 at full 8 MP (3280×2464) needs ~695 Mbit/s per lane. On Pi 3's D-PHY 1.0 (max 1000 Mbit/s/lane), that is 70% utilization — but the sensor's internal readout clock also limits it. Reducing resolution frees both link bandwidth and sensor readout time, enabling higher FPS.

2.5 ISP: From Raw to RGB

Camera sensors output Bayer pattern data — each pixel has only one color (R, G, or B) arranged in a checkerboard:

  ┌──┬──┬──┬──┬──┬──┐
  │ R│ G│ R│ G│ R│ G│     Bayer CFA (Color Filter Array)
  ├──┼──┼──┼──┼──┼──┤     Most common: RGGB
  │ G│ B│ G│ B│ G│ B│
  ├──┼──┼──┼──┼──┼──┤     Each pixel records ONE color.
  │ R│ G│ R│ G│ R│ G│     The ISP reconstructs the other two
  ├──┼──┼──┼──┼──┼──┤     from neighboring pixels.
  │ G│ B│ G│ B│ G│ B│
  └──┴──┴──┴──┴──┴──┘

The Image Signal Processor (ISP) converts raw Bayer data to a usable image:

  Raw Bayer ──► Defect correction ──► Demosaic (Bayer → RGB)
            ──► White balance ──► Color correction matrix
            ──► Gamma ──► Denoise ──► Sharpen ──► Output (RGB/YUV)

On Raspberry Pi, the ISP is a hardware block inside the Broadcom SoC. It is managed by libcamera (not directly accessible from user space). The ISP processes at line rate — no frame-buffer copy needed between ISP stages.

V4L2 vs libcamera

V4L2 (Video4Linux2) is the kernel API for camera devices. It works well for simple USB cameras that output pre-processed frames (MJPEG, YUYV). For MIPI CSI-2 cameras with a hardware ISP, libcamera is the modern choice — it manages the ISP pipeline, 3A algorithms (auto-exposure, auto-white-balance, auto-focus), and sensor tuning files. On Raspberry Pi, libcamera is the only supported camera stack since Pi OS Bullseye.

3. MIPI DSI: Display Interface

DSI carries pixel data from the SoC to a display panel. It uses the same D-PHY physical layer as CSI-2 but adds features for display control.

3.1 Video Mode vs Command Mode

DSI supports two fundamentally different operating modes:

  ┌─────────────────────────────────────────────────────────────┐
  │  VIDEO MODE                                                  │
  │                                                              │
  │  SoC continuously streams frames to the panel.              │
  │  Panel has no frame buffer — must receive data every        │
  │  refresh cycle, like an HDMI monitor.                       │
  │                                                              │
  │  Used by: most embedded panels, the Pi 7" touchscreen       │
  │  Pro: simple panel hardware (cheaper)                        │
  │  Con: constant bandwidth consumption                         │
  ├─────────────────────────────────────────────────────────────┤
  │  COMMAND MODE                                                │
  │                                                              │
  │  Panel has its own frame buffer (RAM inside the panel IC).  │
  │  SoC sends updates only when the image changes.             │
  │                                                              │
  │  Used by: AMOLED phone screens, smart watch displays        │
  │  Pro: saves power when image is static                       │
  │  Con: panel needs built-in RAM (more expensive)              │
  └─────────────────────────────────────────────────────────────┘

The Pi's DSI interface uses Video Mode — the display controller continuously streams pixel data at the configured refresh rate.

3.2 DSI Packet Structure

DSI uses two packet types:

  Short Packet (4 bytes) — commands:
  ┌─────────┬──────────┬─────────────┬─────┐
  │ Data ID │ Data[0]  │ Data[1]     │ ECC │
  │ (8 bit) │ (8 bit)  │ (8 bit)     │(8b) │
  └─────────┴──────────┴─────────────┴─────┘

  Long Packet (6 + N bytes) — pixel data:
  ┌─────────┬────────────┬─────┬──────────────────┬────────┐
  │ Data ID │ Word Count │ ECC │  Payload (N bytes)│ CRC-16 │
  │ (8 bit) │ (16 bit)   │(8b) │                   │(16 bit)│
  └─────────┴────────────┴─────┴──────────────────┴────────┘

Packet Type	Examples
Short: DCS Write (no param)	Sleep In, Sleep Out, Display On/Off
Short: DCS Write (1 param)	Set brightness, set pixel format
Long: Packed Pixel Stream	One line of RGB data
Long: DCS Long Write	Panel configuration sequence

DCS (Display Command Set) is a standardized set of commands for panel initialization. Most DSI panels need a startup sequence (sent in LP mode) before video streaming begins:

  Sleep Out → wait 120 ms → Set Pixel Format (RGB888)
  → Set Column Address → Set Page Address → Display On
  → switch to HS Video Mode → continuous streaming

3.3 Bandwidth Calculation

For the official Pi 7" display (800×480 RGB888 @ 60 FPS) on 2 DSI lanes:

  Pixel data per frame:
    800 × 480 × 24 bits = 9,216,000 bits

  Frames per second:
    9,216,000 × 60 = 552,960,000 bits/s ≈ 553 Mbit/s

  Add blanking and protocol overhead (~20%):
    553 × 1.20 ≈ 664 Mbit/s total

  Per lane (2 lanes):
    664 / 2 ≈ 332 Mbit/s per lane

  D-PHY max: 1000+ Mbit/s per lane → comfortable margin

Display	Resolution	Color	FPS	Lanes	Required BW	Per Lane
Pi 7" touchscreen	800×480	RGB888	60	2	~664 Mbit/s	~332 Mbit/s
Typical phone panel	1080×2400	RGB888	60	4	~4.5 Gbit/s	~1.12 Gbit/s
4K panel (rare emb.)	3840×2160	RGB888	30	4	~8.6 Gbit/s	~2.15 Gbit/s

3.4 Bridge Chips

The Pi's DSI output goes through a TC358762 bridge chip that converts DSI to parallel DPI (RGB) for the panel:

  SoC DSI ──► TC358762 ──► DPI (parallel RGB) ──► LCD panel
              (bridge)      24 data + clk + sync

Why not connect DSI directly to the panel? The 7" panel uses a DPI (parallel) interface internally. The bridge chip translates between the serial (DSI) and parallel (DPI) domains. This is common in embedded — many affordable panels are DPI-native, and bridge chips are cheaper than DSI-native panel controllers.

DPI (Display Parallel Interface)

DPI is the simplest display interface — 24 GPIO pins carry R[7:0], G[7:0], B[7:0] plus pixel clock, HSync, and VSync. No packets, no serialization, no protocol overhead. The trade-off is pin count: 28 pins vs DSI's 6 wires (2 lanes + clock). DPI is used when the panel is physically close to the SoC and pins are available (common on custom SoM boards, rare on dev boards like the Pi).

4. HDMI

HDMI uses a completely different signaling scheme from MIPI.

4.1 TMDS Signaling

HDMI transmits data using TMDS (Transition-Minimized Differential Signaling) — three data channels (one per color: R, G, B) plus one clock channel:

  SoC HDMI TX                              Monitor HDMI RX
  ┌──────────┐  TMDS Ch0 (Blue + sync) ──► ┌──────────┐
  │           │  TMDS Ch1 (Green)       ──► │           │
  │ Encoder   │  TMDS Ch2 (Red)         ──► │ Decoder   │
  │           │  TMDS Clock             ──► │           │
  │           │◄─── DDC (I2C) ─────────────►│  EDID ROM │
  │           │◄─── CEC (optional) ────────►│           │
  │           │     HPD (Hot Plug Detect) ──►│           │
  └──────────┘                              └──────────┘

Each TMDS channel carries 10-bit encoded symbols at the pixel clock rate. The encoding: - 8b/10b (TMDS encoding, not standard 8b/10b): maps 8 data bits to 10-bit symbols that minimize transitions, reducing EMI - The clock channel carries the pixel clock (e.g., 148.5 MHz for 1080p60) - Each data channel: 148.5 MHz × 10 bits = 1.485 Gbit/s

4.2 HDMI Versions and Bandwidth

HDMI Version	Max Link Rate	Max Resolution	Pi Support
HDMI 1.4	10.2 Gbit/s (3 × 3.4 Gbit/s)	4K @ 30 FPS	Pi 3
HDMI 2.0	18.0 Gbit/s (3 × 6.0 Gbit/s)	4K @ 60 FPS	Pi 4
HDMI 2.1	48.0 Gbit/s (4 × 12.0 Gbit/s)	8K @ 60 FPS / 4K @ 120 FPS	Pi 5 (limited)

4.3 EDID: Display Identification

When you plug in an HDMI cable, the SoC reads the monitor's EDID (Extended Display Identification Data) over the DDC channel (I2C at 100 kHz on the HDMI cable's dedicated pins):

  EDID contains:
  ┌────────────────────────────────────────┐
  │ Manufacturer, model, serial            │
  │ Supported resolutions and refresh rates│
  │ Preferred timing (native resolution)   │
  │ Color space and bit depth support      │
  │ Audio capabilities                     │
  │ CEC physical address                   │
  └────────────────────────────────────────┘

You can read the EDID on a Pi:

# Read raw EDID
cat /sys/class/drm/card1-HDMI-A-1/edid | edid-decode

# Or with modetest
modetest -c  # shows connectors with EDID-derived modes

This is how the Pi automatically selects the right resolution — it reads what the monitor supports and picks the best match.

4.4 Bandwidth Example

For 1920×1080 @ 60 FPS, 8-bit RGB:

  Visible pixels:   1920 × 1080 = 2,073,600
  With blanking:    2200 × 1125 = 2,475,000  (HTotal × VTotal)
  Pixel clock:      2,475,000 × 60 = 148,500,000 Hz = 148.5 MHz

  Per TMDS channel: 148.5 MHz × 10 bits = 1.485 Gbit/s
  Total (3 ch):     4.455 Gbit/s
  HDMI 1.4 max:     10.2 Gbit/s → OK

HTotal and VTotal

Display timings include blanking regions (front porch, sync pulse, back porch) inherited from CRT scan timing. For 1080p60: visible is 1920×1080, but the full timing is 2200×1125. The "invisible" pixels (blanking) carry sync signals and give the display controller time to prepare the next line/frame. These blanking intervals consume real bandwidth — you must include them when calculating link utilization.

5. SPI Displays

SPI displays are covered in detail in the Graphics Stack reference (Section 5). Here is the key bandwidth limitation:

  SPI bus max (Pi):   ~32 MHz (practical) to ~50 MHz (aggressive)
  Throughput:         32 Mbit/s (half-duplex, one data line)

  320×240 RGB565 @ 30 FPS:
    320 × 240 × 16 × 30 = 36,864,000 bit/s ≈ 37 Mbit/s
    → Exceeds 32 Mbit/s SPI. Real-world: ~20-25 FPS.

  480×320 RGB565 @ 30 FPS:
    480 × 320 × 16 × 30 = 73,728,000 bit/s ≈ 74 Mbit/s
    → Way beyond SPI. Real-world: ~12-15 FPS.

SPI displays are CPU-driven — the CPU (or DMA engine) must push every pixel over the SPI bus. The GPU's display controller is hardwired to HDMI and DSI outputs. This is the fundamental difference: HDMI and DSI are fed by dedicated hardware scan-out, while SPI competes for CPU and bus bandwidth with your application.

6. Interface Comparison

6.1 Bandwidth Summary

Interface	Max Bandwidth	Typical Config	Effective Throughput
SPI	~50 Mbit/s	1 data line, half-duplex	32–50 Mbit/s
DPI	~1.2 Gbit/s	24 data + clk @ 50 MHz	~1.0 Gbit/s
MIPI DSI (2 lane)	~3 Gbit/s	2 × 1.5 Gbit/s	~2.0 Gbit/s
MIPI CSI-2 (2 lane)	~3 Gbit/s	2 × 1.5 Gbit/s	~2.0 Gbit/s
HDMI 2.0	18 Gbit/s	3 × 6 Gbit/s TMDS	~14.4 Gbit/s

6.2 Feature Comparison

Feature	SPI	DPI	DSI	HDMI	CSI-2
Direction	Bidir (half)	SoC → Panel	SoC → Panel	SoC → Monitor	Sensor → SoC
Wires	4–5	28+	6 (2-lane)	19 (connector)	6 (2-lane)
GPU scan-out	No (CPU)	Yes	Yes	Yes	N/A (input)
Hot-plug	No	No	No	Yes (HPD)	No
Max resolution	~320×240 @ 30	~1080p	1080p+	4K+	8 MP+
Cable length	~10 cm (PCB)	~5 cm (PCB)	~30 cm (FPC)	~15 m	~30 cm (FPC)
Cost	Panel: $3–8	Panel: $10–25	Panel: $15–40	Monitor: $80+	Module: $10–50

6.3 Signal Integrity Considerations

Concern	SPI	DSI/CSI (D-PHY)	HDMI (TMDS)
Impedance control	Not critical (low speed)	100 Ω differential	100 Ω differential
Trace matching	±5 mm OK	±0.5 mm within pair	±2 mm within pair
Ground plane	Recommended	Required	Required
Via transitions	OK	Minimize (stubs add reflections)	Minimize
Max trace length	~15 cm	~10 cm (on PCB)	N/A (cable)
Connector	Pin header	FPC (15-pin ZIF)	HDMI standard

PCB Layout Rule of Thumb

For D-PHY (DSI/CSI): keep differential pairs as short as possible, route them as tightly coupled pairs with a continuous ground reference, and avoid crossing splits in the ground plane. The FPC cables on the Pi are factory-designed for this — the critical routing is inside the SoC and on the camera/display module PCBs.

7. Pi Hardware Reference

7.1 Raspberry Pi 4 (BCM2711)

  ┌──────────────────────────────────────────────────┐
  │  BCM2711                                          │
  │                                                   │
  │  ┌──────────┐   2-lane D-PHY   ┌──────────────┐ │
  │  │ CSI-2 RX │◄─────────────────│ 15-pin FPC   │ │  Camera
  │  │ + ISP    │                   └──────────────┘ │
  │  └──────────┘                                     │
  │                                                   │
  │  ┌──────────┐   2-lane D-PHY   ┌──────────────┐ │
  │  │ DSI TX   │──────────────────►│ 15-pin FPC   │ │  Display
  │  └──────────┘                   └──────────────┘ │
  │                                                   │
  │  ┌──────────┐   TMDS           ┌──────────────┐ │
  │  │ HDMI TX  │──────────────────►│ Micro-HDMI×2 │ │  HDMI 0, 1
  │  │ (×2)     │                   └──────────────┘ │
  │                                                   │
  │  ┌──────────┐   SPI0, SPI1     ┌──────────────┐ │
  │  │ SPI      │──────────────────►│ GPIO header  │ │  SPI display
  │  └──────────┘                   └──────────────┘ │
  └──────────────────────────────────────────────────┘

Port	D-PHY Lanes	Max Speed/Lane	Notes
CSI-2	2	1.0 Gbit/s	Single camera port
DSI	2	1.0 Gbit/s	Single display port
HDMI 0	N/A (TMDS)	HDMI 2.0 (18 Gbit/s)	4K @ 60 or 4K @ 30 + HDR
HDMI 1	N/A (TMDS)	HDMI 2.0 (18 Gbit/s)	Same capability

7.2 Raspberry Pi 5 (BCM2712)

Port	D-PHY Lanes	Max Speed/Lane	Notes
CSI-2 (×2)	2 each	1.5 Gbit/s	Two camera ports (or 1×4-lane)
DSI (×2)	2 each	1.5 Gbit/s	Two display ports (or 1×4-lane)
HDMI 0	N/A (TMDS)	HDMI 2.0 (18 Gbit/s)	4K @ 60
HDMI 1	N/A (TMDS)	HDMI 2.0 (18 Gbit/s)	4K @ 60

Pi 5 adds a second CSI/DSI port and can combine both into a single 4-lane port for higher bandwidth (useful for 4K cameras or high-resolution DSI panels).

8. Bandwidth Math Workshop

Use these formulas for any interface:

Raw pixel bandwidth

BW_pixel = Width × Height × BitDepth × FPS

With blanking (displays only)

BW_total = HTotal × VTotal × BitDepth × FPS

where:
  HTotal = Width + HFrontPorch + HSyncWidth + HBackPorch
  VTotal = Height + VFrontPorch + VSyncWidth + VBackPorch

Protocol overhead

Interface	Overhead Factor	Source
CSI-2	×1.10 to ×1.15	Packet headers, sync codes, line gaps
DSI (video)	×1.15 to ×1.25	Packet headers, blanking, LP transitions
HDMI	×1.25	8b/10b encoding (10/8 = 1.25) + blanking
SPI	×1.0	No protocol overhead (raw pixel stream)

Per-lane requirement

BW_per_lane = BW_total × overhead_factor / num_lanes

Worked Example: Can I Run a 1280×720 Camera at 60 FPS on Pi 4?

  BW_pixel  = 1280 × 720 × 10 (RAW10) × 60 = 552,960,000 bit/s
  Overhead  = × 1.12 (CSI-2)
  BW_total  = 619,315,200 bit/s ≈ 619 Mbit/s
  Per lane  = 619 / 2 = 310 Mbit/s

  Pi 4 CSI max: 1000 Mbit/s per lane
  310 < 1000 → Yes, comfortably.

  Limiting factor: sensor readout speed, not link bandwidth.

Quick Bandwidth Estimator

For a rough estimate: 1080p @ 30 FPS RAW10 ≈ 700 Mbit/s total. Scale linearly for resolution and frame rate. Double for RAW12 vs RAW10 (roughly — 12/10 = 1.2×).

9. Choosing the Right Interface

flowchart TD
    A[Need to display pixels?] -->|Camera input| B{Resolution?}
    A -->|Display output| C{Budget & resolution?}

    B -->|< 2 MP, USB OK| B1[USB camera + V4L2]
    B -->|> 2 MP or low latency| B2[MIPI CSI-2 + libcamera]

    C -->|Tiny panel < 3 inch| D{Frame rate?}
    C -->|7 inch touchscreen| E[DSI — official Pi display]
    C -->|External monitor / TV| F[HDMI]

    D -->|< 20 FPS OK| D1[SPI display — cheapest]
    D -->|> 30 FPS needed| D2[DSI or HDMI]

Decision rules: - Need GPU scan-out? → DSI or HDMI (not SPI) - Need touch? → DSI panel (I2C touch controller) or HDMI + USB touch overlay - Need hot-plug? → HDMI only - Need minimum cost? → SPI ($3 panel) if frame rate is acceptable - Need minimum wires? → DSI or CSI (6 wires vs HDMI's 19 or DPI's 28+) - Need maximum resolution? → HDMI (4K+) - Custom PCB? → consider DPI for lowest component cost (no bridge chip needed)

Course Overview | Reference Index | Graphics Stack

Interface	Direction	On the Pi	Typical Use
MIPI CSI-2	Camera → SoC	15-pin FPC connector	Camera module
MIPI DSI	SoC → Display	15-pin FPC connector	Official 7" touchscreen
HDMI	SoC → Display	Micro-HDMI (Pi 4/5)	External monitors
SPI	SoC → Display	GPIO header	Small TFT panels (2–4")